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Shader-based tessellation to save memory bandwidth in a mobile multimedia processor

Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
Department of Electrical Engineering and Computer Science, KAIST, 373-1 Yuseong-gu, Guseong-dong, Daejeon, Republic of Korea
Computers & Graphics, Volume 33, Issue 5, October 2009, Pages 625-637

@article{chung2009shader,

   title={Shader-based tessellation to save memory bandwidth in a mobile multimedia processor},

   author={Chung, K. and Yu, C.H. and Kim, D. and Kim, L.S.},

   journal={Computers & Graphics},

   volume={33},

   number={5},

   pages={625–637},

   issn={0097-8493},

   year={2009},

   publisher={Elsevier}

}

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In this paper, we propose an architecture of tessellation hardware to save memory bandwidth in a mobile multimedia processor. To reduce the implementation overhead, floating-point computations of tessellation are accelerated by the conventional GPU pipeline, and only tessellation-specific control logic is handled by an additional hardware unit. Tightly coupled with a vertex shader, the additional unit dynamically produces topological configurations and parametric coordinates of refinement patterns in the type of indexed triangle strips for object-level adaptive tessellation. The topological configurations improve the efficiency of the vertex cache so as to avoid redundant shader operations. Since the proposed tessellator is area-efficient and does not require intermediate memory accesses, its architecture is especially appropriate for the mobile environment, which adopts a shared bus and unified external memory architecture. The proposed tessellator is fabricated on a chip using 0.18microm CMOS technology. With 6.2% additional hardware for a dual-core vertex shader, the implemented chip performs 120 Mvertices/s vertex shading and saves memory bandwidth up to 250 times in tessellation.
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