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Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan
Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA – 16802, USA
18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2010

@inproceedings{kestur2010accelerating,

   title={Accelerating the Nonuniform fast Fourier transform using FPGAs},

   author={Kestur, S. and Park, S. and Irick, K.M. and Narayanan, V.},

   booktitle={2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines},

   pages={19–26},

   year={2010},

   organization={IEEE}

}

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We present an FPGA accelerator for the Non-uniform Fast Fourier Transform, which is a technique to reconstruct images from arbitrarily sampled data. We accelerate the compute-intensive interpolation step of the NuFFT Gridding algorithm by implementing it on an FPGA. In order to ensure efficient memory performance, we present a novel FPGA implementation for Geometric Tiling based sorting of the arbitrary samples. The convolution is then performed by a novel Data Translation architecture which is composed of a multi-port local memory, dynamic coordinate-generator and a plug-and-play kernel pipeline. Our implementation is in single-precision floating point and has been ported onto the BEE3 platform. Experimental results show that our FPGA implementation can generate fairly high performance without sacrificing flexibility for various data-sizes and kernel functions. We demonstrate up to 8X speedup and up to 27 times higher performance-per-watt over a comparable CPU implementation and up to 20% higher performance-per-watt when compared to a relevant GPU implementation.
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