Phase Aware Memory Scheduling

C. Sangani, M. Venkatesan, R. Ramesh


   title={Phase Aware Memory Scheduling},

   author={Sangani, Chirag and Venkatesan, Mathangi and Ramesh, Rakesh}


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Computer architecture is at the brink of convergence with the integration of the general-purpose multi-core CPU architecture and the special purpose accelerated graphics architecture (GPU). Semiconductor giants like Intel and AMD have already brought to the market next-generation integrated heterogeneous processors in the form of the Sandy Bridge and the Fusion architecture respectively. However, with the emergence of these integrated heterogeneous processors, key challenges such as power and memory management have gained further prominence. The rate of improvement in DRAM technology is failing to match the increased footprint of applications and the memory bandwidth demanded by multi-processors, a condition referred to as the ”memory wall”. Efficient memory scheduling algorithms are the need of the hour to meet the bandwidth demands of the applications while also guaranteeing the required amount of Memory Level Parallelism (MLP). The problem we have chosen for the project is to characterize the memory access patterns of CPU-GPU combined applications on an integrated heterogeneous processor architecture and propose a memory scheduling algorithm that can efficiently schedule the memory requests to improve the IPC (instructions per cycle) metric of the CPU application and the FPS (frames per second) metric of the GPU application.
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