Analysis of SuperLU Solvers on Intel MIC Architecture

Ahmet Duran, M. Serdar Celebi, Bora Akaydin, Mehmet Tuncel, Figen Oztoprak
Istanbul Technical University, National Center for High Performance Computing of Turkey (UHeM), Istanbul 34469, Turkey
PRACE whitepaper, 2013


   title={Analysis of SuperLU Solvers on Intel{textregistered} MIC Architecture},

   author={Durana, Ahmet and Celebia, M Serdar and Akaydina, Bora and Tuncela, Mehmet and {"O}ztopraka, Figen},



Download Download (PDF)   View View   Source Source   



Intel Xeon Phi is a coprocessor with sixty-one cores in a single chip. The chip has a more powerful FPU that contains 512-bit SIMD registers. Intel Xeon Phi chip can benefit from the algorithms that operate with the large vectors. In this work, sequential, multithreaded and distributed versions of SuperLU solvers are tested on the Intel Xeon Phi using offload programming model and they work well. There are several offload programming alternatives depending on where to place pragma directives. We find that the sequential SuperLU benefited up to 45% performance improvement from the offload programming depending on the sparse matrix type and the size of transferred and processed data. On the other hand, the partitioning method of SuperLU_DIST and SuperLU_MT generates very small sized submatrices. Therefore, we observe that the matrix partitioning method and several other tradeoffs influence their performance via the Xeon Phi architecture.
No votes yet.
Please wait...

* * *

* * *

* * *

HGPU group © 2010-2022 hgpu.org

All rights belong to the respective authors

Contact us: