Exploring Design Space of 3D NVM and eDRAM Caches Using DESTINY Tool (open-source code)

Sparsh Mittal, Matt Poremba, Jeffrey Vetter, Yuan Xie
Oak Ridge National Laboratory (ORNL)
Oak Ridge National Laboratory, Tech. Report no. ORNL/TM-2014/636, 2015


   title={Exploring Design Space of 3D NVM and eDRAM Caches Using DESTINY Tool},


   author={Sparsh Mittal and Matthew Poremba and Jeffrey Vetter and Yuan Xie},

   institution={Oak Ridge National Laboratory, USA},



   keywords={3D technology, die-stacking, SRAM, NVM, eDRAM, PCM, STT-RAM, ReRAM}


To enable the design of large sized caches, novel memory technologies (such as non-volatile memory) and novel fabrication approaches (e.g. 3D stacking) have been explored. The existing modeling tools, however, cover only few memory technologies, CMOS technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 3D (and 2D) cache designs using SRAM, embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM) and phase change RAM (PCM). DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g. latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target etc. DESTINY has been validated against several cache prototypes. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers.
Rating: 2.5/5. From 2 votes.
Please wait...

* * *

* * *

HGPU group © 2010-2021 hgpu.org

All rights belong to the respective authors

Contact us: