OpenCL-Based Design of an FPGA Accelerator for Phase-Based Correspondence Matching
Graduate School of Information Sciences, Tohoku University, Aoba 6-6-05, Aramaki Aza, Aoba, Sendai, Miyagi, 980-8579, Japan
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2015
@article{tatsumi2015opencl,
title={OpenCL-Based Design of an FPGA Accelerator for Phase-Based Correspondence Matching},
author={Tatsumi, Shunsuke and Hariyama, Masanori and Miura, Mamoru and Ito, Koichi and Aoki, Takafumi},
year={2015}
}
This paper proposes a Field Programmable Gate Array (FPGA) implementation of the stereo correspondence matching using Phase-Only Correlation (POC). The use of high-accuracy stereo correspondence matching based on POC makes it possible to measure accurate 3D shape of an object using stereo vision. The drawback of the POC-based approach is its high computational cost. To address this problem, we propose an FPGA implementation of the POC-based correspondence matching. To design the accelerator efficiently, the OpenCL-based design tool is used which allows us to reuse the existing code for Graphics Processing Units (GPUs). Although reusing the OpenCL code for GPUs, optimizing the code for FPGAs is a tough problem because the architectures of GPUs and FPGAs are completely different. The major contribution of this paper is to address the optimization technologies of an OpenCL-based FPGA accelerator. The implementation results demonstrate that the FPGA implementation has the almost same speed as well as much higher energy efficiency.
August 18, 2015 by hgpu
