Wanted: Floating-Point Add Round-off Error instruction

Marat Dukhan, Richard Vuduc, Jason Riedy
School of Computational Science and Engineering, College of Computing, Georgia Institute of Technology, Atlanta, GA
arXiv:1603.00491 [cs.NA], (1 Mar 2016)


   title={Wanted: Floating-Point Add Round-off Error instruction},

   author={Dukhan, Marat and Vuduc, Richard and Riedy, Jason},






We propose a new instruction (FPADDRE) that computes the round-off error in floating-point addition. We explain how this instruction benefits high-precision arithmetic operations in applications where double precision is not sufficient. Performance estimates on Intel Haswell, Intel Skylake, and AMD Steamroller processors, as well as Intel Knights Corner co-processor, demonstrate that such an instruction would improve the latency of double-double addition by up to 55% and increase double-double addition throughput by up to 103%, with smaller, but non-negligible benefits for double-double multiplication. The new instruction delivers up to 2x speedups on three benchmarks that use high-precision floating-point arithmetic: double-double matrix-matrix multiplication, compensated dot product, and polynomial evaluation via the compensated Horner scheme.
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