Optimization of RAID Erasure Coding Algorithms for Intel Xeon Phi
Saint-Petersburg State University, Saint Petersburg, Russia
The 11th IEEE International Conference on Networking, Architecture, and Storage (NAS 2016), 2016
In this work we describe and consider some features of implementing RAID erasure coding algorithms for Intel Xeon Phi coprocessor. We propose some algorithmic and technical improvements of encoding and decoding performance both in native and offload modes. Proposed approaches are designed to maximize the efficiency of Intel MIC architecture. We suggest new approach to Galois fields arithmetic vectorization which allows to achieve high encoding and decoding speed.
August 31, 2016 by hgpu
