A parallel pattern for iterative stencil + reduce
Dep. of Computer Science, University of Pisa, Italy
arXiv:1609.04567 [cs.DC], (15 Sep 2016)
@article{aldinucci2016parallel,
title={A parallel pattern for iterative stencil + reduce},
author={Aldinucci, M. and Danelutto, M. and Drocco, M. and Kilpatrick, P. and Misale, C. and Pezzi, G. Peretti and Torquati, M.},
year={2016},
month={sep},
archivePrefix={"arXiv"},
primaryClass={cs.DC},
doi={10.1007/s11227-016-1871-z}
}
We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.
September 17, 2016 by hgpu
