Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
Inst. for Integrated Syst., Tech. Univ. Munchen, Munich, Germany
In 2009 International Conference on Field Programmable Logic and Applications (August 2009), pp. 138-145
@conference{claus2009optimizing,
title={Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation},
author={Claus, C. and Huitl, R. and Rausch, J. and Stechele, W.},
booktitle={Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on},
pages={138–145},
issn={1946-1488},
year={2009},
organization={IEEE}
}
In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms a comparable software version running on an Intel Core2Duo E8400 core at 3.00 GHz and delivers almost the same execution time compared to an implementation of the Harris corner detector running on an Nvidia GeForce 8800 GTX GPU.
November 27, 2010 by hgpu
