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Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study

Enzo Rucci, Armando De Giusti, Marcelo Naiouf
III-LIDI, CONICET, Facultad de Informatica, Universidad Nacional de La Plata, La Plata (1900), Buenos Aires, Argentina
XXIII Congreso Argentino de Ciencias de la Computacion, 2017

@inproceedings{rucci2017blocked,

   title={Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study},

   author={Rucci, Enzo and De Giusti, Armando Eduardo and Naiouf, Marcelo},

   booktitle={XXIII Congreso Argentino de Ciencias de la Computaci{‘o}n (La Plata, 2017).},

   year={2017}

}

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Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architecture. While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound applications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.
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