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Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level

Anthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, John Kalamatianos, Onur Kayiran, Michael LeBeane, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, Xianwei Zhang, Akshay Jain, Timothy G. Rogers
AMD Research, Advanced Micro Devices, Inc.
24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2018

@article{gutierrezlost,

   title={Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level},

   author={Gutierrez, Anthony and Beckmann, Bradford M. and Dutu, Alexandru and Gross, Joseph and Kalamatianos, John and Kayiran, Onur and LeBeane, Michael and Poremba, Matthew and Potter, Brandon and Puthoor, Sooraj and Sinclair, Matthew D. and Wyse, Mark and Yin, Jieming and Zhang, Xianwei and Jain, Akshay and Rogers, Timothy G.}

}

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Modern GPU frameworks use a two-phase compilation approach. Kernels written in a high-level language are initially compiled to an implementation-agnostic intermediate language (IL), then finalized to the machine ISA only when the target GPU hardware is known. Most GPU microarchitecture simulators available to academics execute IL instructions because there is substantially less functional state associated with the instructions, and in some situations, the machine ISA’s intellectual property may not be publicly disclosed. In this paper, we demonstrate the pitfalls of evaluating GPUs using this higher-level abstraction, and make the case that several important microarchitecture interactions are only visible when executing lower-level instructions. Our analysis shows that given identical application source code and GPU microarchitecture models, execution behavior will differ significantly depending on the instruction set abstraction. For example, our analysis shows the dynamic instruction count of the machine ISA is nearly 2x that of the IL on average, but contention for vector registers is reduced by 3x due to the optimized resource utilization. In addition, our analysis highlights the deficiencies of using IL to model instruction fetching, control divergence, and value similarity. Finally, we show that simulating IL instructions adds 33% error as compared to the machine ISA when comparing absolute runtimes to real hardware.
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