Double-precision FPUs in High-Performance Computing: an Embarrassment of Riches?

Jens Domke, Kazuaki Matsumura, Mohamed Wahib, Haoyu Zhang, Keita Yashima, Toshiki Tsuchikawa, Yohei Tsuji, Artur Podobas, Satoshi Matsuoka
Global Scientific Information and Computing Center, Tokyo Institute of Technology
arXiv:1810.09330 [cs.DC], (22 Oct 2018)


   title={Double-precision FPUs in High-Performance Computing: an Embarrassment of Riches?},

   author={Domke, Jens and Matsumura, Kazuaki and Wahib, Mohamed and Zhang, Haoyu and Yashima, Keita and Tsuchikawa, Toshiki and Tsuji, Yohei and Podobas, Artur and Matsuoka, Satoshi},






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Among the (uncontended) common wisdom in High-Performance Computing (HPC) is the applications’ need for large amount of double-precision support in hardware. Hardware manufacturers, the TOP500 list, and (rarely revisited) legacy software have without doubt followed and contributed to this view. In this paper, we challenge that wisdom, and we do so by exhaustively comparing a large number of HPC proxy application on two processors: Intel’s Knights Landing (KNL) and Knights Mill (KNM). Although similar, the KNM and KNL architecturally deviate at one important point: the silicon area devoted to double-precision arithmetic’s. This fortunate discrepancy allows us to empirically quantify the performance impact in reducing the amount of hardware double-precision arithmetic. Our analysis shows that this common wisdom might not always be right. We find that the investigated HPC proxy applications do allow for a (significant) reduction in double-precision with little-to-no performance implications. With the advent of a failing of Moore’s law, our results partially reinforce the view taken by modern industry (e.g. upcoming Fujitsu ARM64FX) to integrate hybrid-precision hardware units.
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