Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite
Department of Computer Science and Paderborn Center for Parallel Computing (PC2), Paderborn University, Paderborn, Germany
arXiv:2004.11059 [cs.DC], (23 Apr 2020)
@misc{meyer2020evaluating,
title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite},
author={Marius Meyer and Tobias Kenter and Christian Plessl},
year={2020},
eprint={2004.11059},
archivePrefix={arXiv},
primaryClass={cs.DC}
}
FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high quality of results. There is however no high-level benchmark suite available which specifically enables a comparison of FPGA architectures, programming tools and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards and development tool flows, track progress over time and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.
April 26, 2020 by hgpu
