SOFF: An OpenCL High-Level Synthesis Framework for FPGAs

Gangwon Jo, Heehoon Kim, Jeesoo Lee, Jaejin Lee
ManyCoreSoft, Seoul 08826, Korea
ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020


   title={SOFF: An OpenCL High-Level Synthesis Framework for FPGAs},

   author={Jo, Gangwon and Kim, Heehoon and Lee, Jeesoo and Lee, Jaejin},



Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor performance and usability. This paper proposes a highlevel synthesis framework of OpenCL for FPGAs, called SOFF. It automatically synthesizes a datapath to execute many OpenCL kernel threads in a pipelined manner. It also synthesizes an efficient memory subsystem for the datapath based on the characteristics of OpenCL kernels. Unlike previous high-level synthesis techniques, we propose a formal way to handle variablelatency instructions, complex control flows, OpenCL barriers, and atomic operations that appear in real-world OpenCL kernels. SOFF is the first OpenCL framework that correctly compiles and executes all applications in the SPEC ACCEL benchmark suite except three applications that require more FPGA resources than are available. In addition, SOFF achieves the speedup of 1.33 over Intel FPGA SDK for OpenCL without any explicit user annotation or source code modification.
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