Data transformations enabling loop vectorization on multithreaded data parallel architectures
Department of ECE, Northeastern University, Boston, MA 02115 USA
In PPoPP ’10: Proceedings of the 15th ACM SIGPLAN symposium on Principles and practice of parallel computing (2010), pp. 353-354.
@conference{jang2010data,
title={Data transformations enabling loop vectorization on multithreaded data parallel architectures},
author={Jang, B. and Mistry, P. and Schaa, D. and Dominguez, R. and Kaeli, D.},
booktitle={Proceedings of the 15th ACM SIGPLAN symposium on Principles and practice of parallel computing},
pages={353–354},
year={2010},
organization={ACM}
}
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memory access patterns in the data stream. This paper describes data transformations that allow us to vectorize loops targeting massively multithreaded data parallel architectures. We present a mathematical model that captures loop-based memory access patterns and computes the most appropriate data transformations in order to enable vectorization. Our experimental results show that the proposed data transformations can significantly increase the number of loops that can be vectorized and enhance the data-level parallelism of applications. Our results also show that the overhead associated with our data transformations can be easily amortized as the size of the input data set increases. For the set of high performance benchmark kernels studied, we achieve consistent and significant performance improvements (up to 11.4X) by applying vectorization using our data transformation approach.
January 7, 2011 by hgpu
