25659

HLS Portability from Intel to Xilinx: A Case Study

Zhili Xiao, Roger D. Chamberlain, Anthony M. Cabrera
Department of Computer Science and Engineering, Washington University in St. Louis, St. Louis, Missouri, USA
IEEE High-Performance Extreme Computing Conference (HPEC), 2021

@article{xiao2021hls,

   title={HLS Portability from Intel to Xilinx: A Case Study},

   author={Xiao, Zhili and Chamberlain, Roger D and Cabrera, Anthony M},

   year={2021}

}

Field-programmable gate arrays (FPGAs) are a hardware accelerator option that is growing in popularity. However, FPGAs are notoriously hard to program. To this end, high-level synthesis (HLS) tools have been developed to allow programmers to design hardware accelerators with FPGAs using familiar software languages. The two largest FPGA vendors, Intel and Xilinx, support both C/C++ and OpenCL C to construct kernels. However, little is known about the portability of designs between these two platforms. In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We conduct a case study, porting the Needleman-Wunsch application from the Rodinia benchmark suite written in Intel OpenCL C to Xilinx platforms. We use OpenCL C kernels optimized for Intel FPGA platforms as a starting point and first perform a minimum effort port to a Xilinx FPGA, also using OpenCL C. We find that simply porting one-toone optimizations is not enough to enable portable performance. We then seek to improve the performance of those kernels using Xilinx C/C++. With rewriting the kernel for burst transfer and other optimizations, we are able to reduce the execution time from an initial 294 s to 2.2 s.
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