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Efficient OpenCL system integration of non-blocking FPGA accelerators

Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen
Tampere University, Tampere, Finland
Microprocessors and Microsystems, Volume 97, 104772, 2023

@article{leppanen2023efficient,

   title={Efficient OpenCL system integration of non-blocking FPGA accelerators},

   author={Lepp{"a}nen, Topi and Lotvonen, Atro and Mousouliotis, Panagiotis and Multanen, Joonas and Keramidas, Georgios and J{"a}{"a}skel{"a}inen, Pekka},

   journal={Microprocessors and Microsystems},

   pages={104772},

   year={2023},

   publisher={Elsevier}

}

OpenCL functions as a portability layer for diverse heterogeneous hardware platforms including CPUs, GPUs, FPGAs, and hardware accelerators. However, OpenCL programs utilizing multiple of these devices in the same computing platform suffer from poor coordination between OpenCL implementations of different hardware vendors. This paper proposes a vendor-independent open source method for integrating custom FPGA accelerators into a common OpenCL platform. The accelerators are wrapped in a common hardware interface to enable efficient synchronization and data sharing between devices on the same chip. The provided software connects the accelerator to OpenCL runtime and enables the control of diverse FPGA accelerators with OpenCL command queues. The benefits of the integration methodology are demonstrated by creating FPGA accelerators with different development tools and integrating them together on two different types of FPGA devices while showing minimal integration overhead. Direct memory access of the accelerator to external memory is shown to increase the performance by a factor of 8. Non-blocking execution enabled by the on-chip synchronization between devices is shown to remove a 250 us overhead from dependent kernel launches. Additionally, as a proof of concept and a case study, a fully OpenCL-controllable computing platform with two devices is implemented on an FPGA to compute CNN inference on a real-world input signal.
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