Static Memory Access Pattern Analysis on a Massively Parallel GPU
Computer Architecture Labratory, Northeastern University, Boston, MA 02188 USA
Symposium on Application Accelerators in High Performance Computing, 2010
@article{jang2010static,
title={Static Memory Access Pattern Analysis on a Massively Parallel GPU},
author={Jang, B. and Schaa, D. and Mistry, P. and Kaeli, D.},
booktitle={Application Accelerators in High Performance Computing, 2010 Symposium, Papers},
year={2010}
}
The performance of data-parallel processing can be highly sensitive to any contention in memory. In contrast to multi-core CPUs which employ a number of memory latency minimization techniques such as multi-level caching and prefetching, Graphics Processing Units (GPUs) require that the data-parallel computations reference memory in a deterministic pattern in order to reap the benefits of these many-core platforms. Memory access sensitivity is primarily due to the Massively Parallel Processing (MPP) execution model and underlying memory hardware architecture of GPUs which are specifically tuned for graphics rendering [2, 4]. In this paper we present a static memory access pattern analysis model that provides guidance on how best to apply a wide range of memory optimizations on GPUs. Our analysis carefully takes into account the mapping of threads to data, a critical factor when attempting to exploit the full capabilities of current GPU architectures. We formulate a methodology that allows us to build tools to guide programmers on how best to apply algorithmic memory optimizations and can easily be integrated into a pass of a compiler. We demonstrate the power of our analysis model by showing a case study of a matrix multiplication implementation using the OpenCL programming language on NVIDIA G80 and G200 series GPUs which have slightly different memory architectures.
February 16, 2011 by hgpu
