GPU Accelerated VLSI Design Verification
Institute of Microelectronics, Tsinghua University, Beijing, China
2010 10th IEEE International Conference on Computer and Information Technology (2010) Issue: Cit, Publisher: Ieee, Pages: 1213-1218
@conference{deng2010gpu,
title={GPU Accelerated VLSI Design Verification},
author={Deng, Y.S.},
booktitle={2010 10th IEEE International Conference on Computer and Information Technology (CIT 2010)},
pages={1213–1218},
year={2010},
organization={IEEE}
}
Today’s Very Large Scale Integrated-Circuit (VLSI) designs require intensive verification effort. However, traditional sequential verification solutions could no longer provide the scalability for future large designs. The so-called verification gap hinders the development of future VLSI products. In this paper, we review our recent works on accelerating typical VLSI verification tasks with modern GPUs. Our works prove that the potential of GPUs can be effectively unleashed through designing efficient data parallel algorithms and/or re-structuring existing sequential algorithms.
March 21, 2011 by hgpu
