high performance computing on graphics processing units: hgpu.org

This thesis explores the possibility of mapping power flow algorithms on a graphics processor. In particular we demonstrate the implementation of DC power flow based contingency analysis on a graphic processing unit (GPU). GPU’s are SIMD processors with highly streamlined architecture to support rendering of graphic images on the computer screen. However, in the recent decade, there has been great interest in exploiting the GPU architecture for purposes beyond rendering of graphic images. Mapping power flow algorithm to this processor is one such attempt. Contingency analysis for power systems is a computationally exhaustive process, but at the same time is a valuable exercise for power system engineers in order to ensure power system security under various operating conditions. Numerous previous attempts have been made to efficiently implement the contingency algorithm on various high performance architectures, however there has been no attempt to implement the algorithm on a Graphics processor. There are numerous advantages to such an implementation, which is outlined in the thesis. In particular following has been accomplished as part of the research work leading up to this thesis. 1. Modeling the DC power flow based contingency analysis algorithm to align with the highly pipelined architecture of GPU. 2. Optimizing the algorithm to enable efficient use of the GPU architecture and exploiting the inherent sparsity of Power system matrices. 3. Implementation of the algorithm. 4. Analysis of the speedup achieved as a result of change in system size. In essence we have demonstrated that power system algorithms could be successfully implemented on the GPU’s. Further research would be required to take advantage of the advances in the graphics computing industry, along with further streamlining of the algorithm to achieve higher throughput.