SHARC: A streaming model for FPGA accelerators and its application to Saliency

Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan
Microsystems Design Laboratory (MDL), Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA – 16802, USA
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011


   title={SHARC: A streaming model for FPGA accelerators and its application to Saliency},

   author={Kestur, S. and Dantara, D. and Narayanan, V.},

   booktitle={Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011},





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Reconfigurable hardware such as FPGAs are being increasingly employed for accelerating compute-intensive applications. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. We present SHARC – Streaming Hardware Accelerator with Run-time Configurability, for an FPGA-based accelerator. This model is at a lower-level compared to existing stream processing models and provides the hardware designer with a flexible platform for developing custom accelerators. The SHARC model provides a generic interface for each hardware module and a hierarchical structure for parallelism at multiple levels in an accelerator. It also includes a parameterization and hierarchical run-time reconfiguration framework to enable hardware reuse for flexible yet high throughput design. This model is very well suited for compute-intensive applications in areas such as real-time vision and signal processing, where stream processing provides enormous performance benefits. We present a case-study by implementing a bio-inspired Saliency-based visual attention system using the proposed model and demonstrate the benefits of run-time reconfiguration. Experimental results show about 5X speedup over an existing CPU implementation and up to 14X higher Performance-per-Watt over a relevant GPU implementation.
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