Efficient floating-point texture decompression
Nokia Res. Center, Tampere, Finland
International Symposium on System on Chip (SoC), 2010
@inproceedings{aarnio2010efficient,
title={Efficient floating-point texture decompression},
author={Aarnio, T. and Brunelli, C. and Viitanen, T.},
booktitle={System on Chip (SoC), 2010 International Symposium on},
pages={31–34},
year={2010},
organization={IEEE}
}
We propose a novel hardware design for decoding compressed floating-point textures in a graphics processing unit (GPU). Our decoder is based on the NXR texture format, which provides lossy, fixed-rate 6:1 compression for floating-point textures. Our design exploits the constraints of the compressed pixel blocks to produce the correct output using only fixed-point arithmetic. This results in significantly lower silicon area occupation compared to pre-existing floating-point texture decoders.
August 31, 2011 by hgpu
