Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
University of California, Berkeley, Berkeley, CA, USA
Proceeding of the 38th annual international symposium on Computer architecture, ISCA ’11, 2011
@inproceedings{lee2011exploring,
title={Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators},
author={Lee, Y. and Avizienis, R. and Bishara, A. and Xia, R. and Lockhart, D. and Batten, C. and Asanovic, K.},
booktitle={Proceedings of the 38th Annual International Symposium on Computer Achitecture, ISCA},
volume={11},
year={2011}
}
We present a taxonomy and modular implementation approach for data-parallel accelerators, including the MIMD, vector-SIMD, subword-SIMD, SIMT, and vector-thread (VT) architectural design patterns. We have developed a new VT microarchitecture, Maven, based on the traditional vector-SIMD microarchitecture that is considerably simpler to implement and easier to program than previous VT designs. Using an extensive design-space exploration of full VLSI implementations of many accelerator design points, we evaluate the varying tradeoffs between programmability and implementation efficiency among the MIMD, vector-SIMD, and VT patterns on a workload of microbenchmarks and compiled application kernels. We find the vector cores provide greater efficiency than the MIMD cores, even on fairly irregular kernels. Our results suggest that the Maven VT microarchitecture is superior to the traditional vector-SIMD architecture, providing both greater efficiency and easier programmability.
September 7, 2011 by hgpu
