Multicore performance optimization using partner cores

Eric Lau, Jason E. Miller, Inseok Choi, Donald Yeung, Saman Amarasinghe, Anant Agarwal
MIT Computer Science and Artificial Intelligence Laboratory
Proceedings of the 3rd USENIX conference on Hot topic in parallelism, HotPar’11, 2011


   title={Multicore Performance Optimization Using Partner Cores},

   author={Lau, E. and Miller, J.E. and Choi, I. and Yeung, D. and Amarasinghe, S. and Agarwal, A.},

   booktitle={3rd USENIX conference on Hot topic in parallelism, HotPar’11},



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As the push for parallelism continues to increase the number of cores on a chip, system design has become incredibly complex; optimizing for performance and power efficiency is now nearly impossible for the application programmer. To assist the programmer, a variety of techniques for optimizing performance and power at runtime have been developed, but many employ the use of speculative threads or performance counters. These approaches result in stolen cycles, or the use of an extra core, and such expensive penalties can greatly reduce the potential gains. At the same time that general purpose processors have grown larger and more complex, technologies for smaller embedded processors have pushed towards energy efficiency. In this paper, we combine the two and introduce the concept of Partner Cores: low-area, low-power cores paired with larger, faster compute cores. A partner core is tightly coupled to each main processing core, allowing it to perform various optimizations and functions that are impossible on a traditional chip multiprocessor. This paper demonstrates that optimization code running on a partner core can increase performance and provide a net improvement in power efficiency.
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