May, 20

OpenCL Vector Swizzling Optimization under Global Value Numbering

Under Heterogeneous System Architecture (HSA), each device work together to improve performance. Open Computing Language (OpenCL) provides functionalities to complete parallel computing in different devices. OpenCL vector bundles identical data types and operates them meanwhile. However, optimization upon vector swizzling becomes difficult due to vector swizzling operations with several OpenCL vectors. In this paper, new […]
May, 12

Dwarfs on Accelerators: Enhancing OpenCL Benchmarking for Heterogeneous Computing Architectures

For reasons of both performance and energy efficiency, high-performance computing (HPC) hardware is becoming increasingly heterogeneous. The OpenCL framework supports portable programming across a wide range of computing devices and is gaining influence in programming next-generation accelerators. To characterize the performance of these devices across a range of applications requires a diverse, portable and configurable […]
May, 12

Efficient Hardware Acceleration on SoC-FPGA with OpenCL

Field Programmable Gate Arrays (FPGAs) are taking over the conventional processors in the field of High Performance computing. With the advent of FPGA architectures and High level synthesis tools, FPGAs can now be easily used to accelerate computationally intensive applications like, e.g., AI and Cognitive computing. One of the advantages of raising the level of […]
May, 5

Simulating Quantum Computers Using OpenCL

I present QCGPU, an open source Rust library for simulating quantum computers. QCGPU uses the OpenCL framework to enable acceleration by devices such as GPUs, FPGAs and DSPs. I perform a number of optimizations including parallelizing operations such as the application of gates and the calculation of various state probabilities for the purpose of measurment. […]
Apr, 15

Automatic Optimization of OpenCL-Based Stencil Codes for FPGAs and Its Evaluation

Recently, C-based OpenCL design environment is proposed to design FPGA (field programmable gate array) accelerators. Although many C-programs can be executed on FPGAs, the best c-code for a CPU may not be the most appropriate one for an FPGA. Users must have some knowledge about computer architecture in order to write a good OpenCL code. […]
Mar, 31

A Comparison between GPU-based Volume Ray Casting Implementations: Fragment Shader, Compute Shader, OpenCL, and CUDA

Volume rendering is an important area of study in computer graphics, due to its application in areas such as medicine, physic simulations, oil and gas industries, and others. The main used method nowadays for volume rendering is ray casting. Nevertheless, there are a variety of parallel APIs that can be used to implement it. Thus, […]
Mar, 22

FPGA in HPC: High Level Synthesys of OpenCL kernels for Molecular Dynamics

The overall goal of this thesis is to evaluate the feasibility of FPGA based computer system in HPC. This works is performed within ExaNeSt, an EU funded project which aims to develop and prototype energy efficient solutions for the production of exascale-level supercomputers. As the matter of fact, the current computer architectures need to be […]
Mar, 17

Improved OpenCL-based Implementation of Social Field Pedestrian Model

Two aspects of improvements are proposed for the OpenCL-based implementation of the social field pedestrian model. In the aspect of algorithm, a method based on the idea of divide-and-conquer is devised in order to overcome the problem of global memory depletion when fields are of a larger size. This is of importance for the study […]
Mar, 10

Portable Real-Time DCT Based Steganography Using OpenCL

In this paper a steganographic method for real time data hiding is proposed. The main goal of the research is to develop steganographic method with increased robustness to unintentional image processing attacks. In addition, we prove the validity of the method in real time applications. The method is based on a discrete cosine transform (DCT) […]
Mar, 10

OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing

Field programmable gate arrays (FPGAs) have gained attention in high-performance computing (HPC) research because their computation and communication capabilities have dramatically improved in recent years as a result of improvements to semiconductor integration technologies that depend on Moore’s Law. In addition to FPGA performance improvements, OpenCL-based FPGA development toolchains have been developed and offered by […]
Mar, 3

OpenCL Acceleration for TensorFlow

There is huge demand for targeting complex and large-scale machine learning applications particularly those based on popular actively-maintained frameworks such as TensorFlow and CAFFE to a variety of platforms with accelerators ranging from high-end desktop GPUs to resource-constrained embedded or mobile GPUs, FPGAs, and DSPs. However, to deliver good performance different platforms may require different […]
Feb, 9

Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL

Recent developments in High Level Synthesis tools have attracted software programmers to accelerate their high-performance computing applications on FPGAs. Even though it has been shown that FPGAs can compete with GPUs in terms of performance for stencil computation, most previous work achieve this by avoiding spatial blocking and restricting input dimensions relative to FPGA on-chip […]
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