10858

Comparative Performance Analysis of Intel Xeon Phi, GPU, and CPU

George Teodoro, Tahsin Kurc, Jun Kong, Lee Cooper, Joel Saltz
Department of Computer Science, University of Brasilia, Brasilia, DF, Brazil
arXiv:1311.0378 [cs.DC], (2 Nov 2013)
@article{2013arXiv1311.0378T,

   author={Teodoro}, G. and {Kurc}, T. and {Kong}, J. and {Cooper}, L. and {Saltz}, J.},

   title={"{Comparative Performance Analysis of Intel Xeon Phi, GPU, and CPU}"},

   journal={ArXiv e-prints},

   archivePrefix={"arXiv"},

   eprint={1311.0378},

   primaryClass={"cs.DC"},

   keywords={Computer Science – Distributed, Parallel, and Cluster Computing, Computer Science – Performance, C.4, D.1.3, D.2.6},

   year={2013},

   month={nov},

   adsurl={http://adsabs.harvard.edu/abs/2013arXiv1311.0378T},

   adsnote={Provided by the SAO/NASA Astrophysics Data System}

}

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We investigate and characterize the performance of an important class of operations on GPUs and Many Integrated Core (MIC) architectures. Our work is motivated by applications that analyze low-dimensional spatial datasets captured by high resolution sensors, such as image datasets obtained from whole slide tissue specimens using microscopy image scanners. We identify the data access and computation patterns of operations in object segmentation and feature computation categories. We systematically implement and evaluate the performance of these core operations on modern CPUs, GPUs, and MIC systems for a microscopy image analysis application. Our results show that (1) the data access pattern and parallelization strategy employed by the operations strongly affect their performance. While the performance on a MIC of operations that perform regular data access is comparable or sometimes better than that on a GPU; (2) GPUs are significantly more efficient than MICs for operations and algorithms that irregularly access data. This is a result of the low performance of the latter when it comes to random data access; (3) adequate coordinated execution on MICs and CPUs using a performance aware task scheduling strategy improves about 1.29x over a first-come-first-served strategy. The example application attained an efficiency of 84% in an execution with of 192 nodes (3072 CPU cores and 192 MICs).
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