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Design of an FPGA-Based FDTD Accelerator Using OpenCL

Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Graduate School of Information Sciences, Tohoku University, Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’14), pp.371-375, 2014

@article{takei2014design,

   title={Design of an FPGA-Based FDTD Accelerator Using OpenCL},

   author={Takei, Yasuhiro and Waidyasooriya, Hasitha Muthumala and Hariyama, Masanori and Kameyama, Michitaka},

   year={2014}

}

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High-performance computing systems with dedicated hardware on FPGAs can achieve power efficient computations compared with CPUs and GPUs. However, the hardware design on FPGAs needs more time than the software design on CPUs and GPUs. We designed an FDTD hardware accelerator using the OpenCL compiler for FPGAs in this paper. Since it is possible to design a hardware automatically from an OpenCL code, we can implement applications on FPGAs in a short time compared with the design by using a hardware description language. According to the result of the implementation of the FDTD accelerator on the FPGA, the processing speed is faster than a CPU. Moreover, its power consumption is about one-tenth of a GPU.
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