A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization

Jordi Roca, Victor Moya, Carlos Gonzalez, Vicente Escandell, Albert Murciego, Agustin Fernandez, Roger Espasa
Computer Architecture Department (UPC), Barcelona, Spain
The Visual Computer, Vol. 26, No. 6. (1 June 2010), pp. 707-719.


   title={A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization},

   author={Roca, J. and Moya, V. and Gonzalez, C. and Escandell, V. and Murciego, A. and Fernandez, A. and Espasa, R.},

   journal={The Visual Computer},








Download Download (PDF)   View View   Source Source   



This paper shows that breaking the barrier of 1 triangle/clock rasterization rate for microtriangles in modern GPU architectures in an efficient way is possible. The fixed throughput of the special purpose culling and triangle setup stages of the classic pipeline limits the GPU scalability to rasterize many triangles in parallel when these cover very few pixels. In contrast, the shader core counts and increasing GFLOPs in modern GPUs clearly suggests parallelizing this computation entirely across multiple shader threads, making use of the powerful wide-ALU instructions. In this paper, we present a very efficient SIMD-like rasterization code targeted at very small triangles that scales very well with the number of shader cores and has higher performance than traditional edge equation based algorithms. We have extended the ATTILA GPU shader ISA (del Barrioet al. in IEEE International Symposium on Performance Analysis of Systems and Software, pp.231-241, 2006) with two fixed point instructions to meet the rasterization precision requirement. This paper also introduces a novel subpixel Bounding Box size optimization that adjusts the bounds much more finely, which is critical for small triangles, and doubles the 2?2-pixel stamp test efficiency. The proposed shader rasterization program can run on top of the original pixel shader program in such a way that selected fragments are rasterized, attribute interpolated and pixel shaded in the same pass. Our results show that our technique yields better performance than a classic rasterizer at 8 or more shader cores, with speedups as high as 4? for 16 shader cores.
No votes yet.
Please wait...

* * *

* * *

HGPU group © 2010-2017 hgpu.org

All rights belong to the respective authors

Contact us: