2820

Increasing Memory Miss Tolerance for SIMD Cores

David Tarjan, Jiayuan Meng and Kevin Skadron
Department of Computer Science, University of Virginia, Charlottesville, VA 22904
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2009, SC ’09

@conference{tarjan2009increasing,

   title={Increasing memory miss tolerance for SIMD cores},

   author={Tarjan, D. and Meng, J. and Skadron, K.},

   booktitle={Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis},

   pages={1–11},

   year={2009},

   organization={ACM}

}

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Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “diverge on miss” that allows SIMD cores to better tolerate memory latency for workloads with non-contiguous memory access patterns. Individual threads within a SIMD “warp” are allowed to slip behind other threads in the same warp, letting the warp continue execution even if a subset of threads are waiting on memory. Diverge on miss can either increase the performance of a given design by up to a factor of 3.14 for a single warp per core, or reduce the number of warps per core needed to sustain a given level of performance from 16 to 2 warps, reducing the area per core by 35%.
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