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Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators

Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch
Embedded Systems and Applications Group, Technische Universitat Darmstadt, Darmstadt, Germany
International Conference on Embedded Computer Systems (SAMOS), 2010

@inproceedings{huthmann2010accelerating,

   title={Accelerating high-level engineering computations by automatic compilation of geometric algebra to hardware accelerators},

   author={Huthmann, J. and Muller, P. and Stock, F. and Hildenbrand, D. and Koch, A.},

   booktitle={Embedded Computer Systems (SAMOS), 2010 International Conference on},

   pages={216–222},

   year={2010},

   organization={IEEE}

}

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Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to engineering problems. The actual evaluation of GA expressions, though, is extremely compute intensive due to the high-dimensionality of data being processed. On standard desktop CPUs, GA evaluations take considerably longer than conventional mathematical formulations. GPUs do offer sufficient throughput to make the use of concise GA formulations practical, but require power far exceeding the budgets for most embedded applications. While the suitability of low-power reconfigurable accelerators for evaluating specific GA computations has already been demonstrated, these often required a significant manual design effort. We present a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate accelerators from the abstract GA descriptions without user intervention that are suitable for high-performance embedded computing.
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