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A balanced programming model for emerging heterogeneous multicore systems

Wei Liu, Brian Lewis, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Sai Luo, Bratin Saha
Intel Corporation
Proceedings of the 2nd USENIX conference on Hot topics in parallelism, HotPar’10, 2010

@inproceedings{liu2010balanced,

   title={A balanced programming model for emerging heterogeneous multicore systems},

   author={Liu, W. and Lewis, B. and Zhou, X. and Chen, H. and Gao, Y. and Yan, S. and Luo, S. and Saha, B.},

   booktitle={Proceedings of the 2nd USENIX conference on Hot topics in parallelism},

   pages={3–3},

   year={2010},

   organization={USENIX Association}

}

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Computer systems are moving towards a heterogeneous architecture with a combination of one or more CPUs and one or more accelerator processors. Such heterogeneous systems pose a new challenge to the parallel programming community. Languages such as OpenCL and CUDA provide a program environment for such systems. However, they focus on data parallel programming where the majority of computation is carried out by the accelerators. Our view is that, in the future, accelerator processors will be tightly coupled with the CPUs, be available in different system architectures (e.g., integrated and discrete), and systems will be dynamically reconfigurable. In this paper we advocate a balanced programming model where computation is balanced between the CPU and its accelerators. This model supports sharing virtual memory between the CPU and the accelerator processors so the same data structures can be manipulated by both sides. It also supports task-parallel as well as data-parallel programming, fine-grained synchronization, thread scheduling, and load balancing. This model not only leverages the computational capability of CPUs, but also allows dynamic system reconfiguration, and supports different platform configurations. To help demonstrate the practicality of our programming model, we present performance results for a preliminary implementation on a computer system with an Intel
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