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A prototyping environment for high performance reconfigurable computing

George Afonso, Rabie Ben Atitallah, Alexandre Loyer, Jean-Luc Dekeyser, Nicolas Belanger, Martial Rubio
EADS Innovation Works, INRIA Lille-Nord Europe
6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011

@inproceedings{afonso2011prototyping,

   title={A prototyping environment for high performance reconfigurable computing},

   author={Afonso, G. and Dekeyser, J.L. and Ben Atitallah, R. and Belanger, N. and Loyer, A. and Rubio, M.},

   booktitle={Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on},

   pages={1–8},

   organization={IEEE},

   year={2011}

}

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In the face of power wall and high performance requirements, designers of hardware architectures are directed more and more towards reconfigurable computing with the usage of heterogeneous CPU/FPGA systems. In such architectures, multi-core processors come with high computation rates while the reconfigurable logic offers high performance per watt and adaptability to the application constraints. However, the design of heterogeneous architectures is facing extremely challenging requirements such as the appropriate programming model, design tools, and the rapid system prototyping. Focusing this issue, we present a prototyping environment for heterogeneous CPU/FPGA systems. Within this environment, we conceived a generic and scalable architecture based on a multi-core processor tightly-connected to FPGA in order to meet performance, power and flexibility goals. Furthermore, front-end interfaces are presented in order to establish communication, data sharing, and synchronisation between the different software and hardware processing units. Finally, we defined a design methodology that eases the development of applications onto heterogeneous systems. Our environment is conceived using standard host machine coupled with a Xilinx Virtex 6 FPGA through the PCI Express standard bus. In the experimental part, we evaluate first the reliability of different CPU/FPGA communication solutions in order to bring real-time capabilities to our system. Secondly, we demonstrate the efficiency of the presented design methodology for heterogeneous systems through the FIR signal processing application.
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