8476

Reusable OpenCL FPGA Infrastructure

Stephen Alexander Chin
Graduate Department of Electrical and Computer Engineering, University of Toronto
University of Toronto, 2012
@phdthesis{chin2012reusable,

   title={Reusable OpenCL FPGA Infrastructure},

   author={Chin, S.A.},

   year={2012},

   school={University of Toronto}

}

Download Download (PDF)   View View   Source Source   

1179

views

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element – the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.
VN:F [1.9.22_1171]
Rating: 0.0/5 (0 votes cast)

* * *

* * *

Follow us on Twitter

HGPU group

1863 peoples are following HGPU @twitter

Like us on Facebook

HGPU group

406 people like HGPU on Facebook

HGPU group © 2010-2016 hgpu.org

All rights belong to the respective authors

Contact us: