Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters

Gabriel Falcao, Joao Andrade, Vitor Silva, Shinichi Yamagiwa, Leonel Sousa
Instituto de Telecomunicacoes, University of Coimbra, Portugal
10th International Symposium on Wireless Communication Systems (ISWCS), 2013


   title={Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters},

   author={Yamagiwa, Shinichi and PRESTO, JST},



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Low-Density Parity-Check (LDPC) codes are known for having excellent Bit Error Rate (BER) performance, even in the presence of quite low Signal-to-Noise Ratios (SNR). But the development of this type of error-correcting codes poses severe challenges since the design of new codes is based on heuristics such as girth and sparsity that not always provide the expected BER results and, consequently, can take long periods of time to be tested with Monte Carlo simulations using a massive amount of bits pseudo-randomly generated and transmitted over noisy channels. We address the computational complexity demanded by the LDPC decoder and the challenges imposed from the parallel architecture perspective, in particular targeting multicore systems that have the potential to deal more efficiently with computationally intensive applications. To handle the massive computational power required by the new and computationally more intensive generations of LDPC codes that demand lower error floors, namely optical communication ones, we propose using clusters of GPUs as a way to accelerate this type of Monte Carlo simulations from years or months to weeks or days.
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