Optimal loop unrolling for GPGPU programs
Dept. of Comput. Sci. & Eng., Ohio State Univ., Columbus, OH, USA
In 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS) (April 2010), pp. 1-11.
@conference{murthy2010optimal,
title={Optimal loop unrolling for GPGPU programs},
author={Murthy, G.S. and Ravishankar, M. and Baskaran, M.M. and Sadayappan, P.},
booktitle={Parallel & Distributed Processing (IPDPS), 2010 IEEE International Symposium on},
pages={1–11},
issn={1530-2075},
year={2010},
organization={IEEE}
}
Graphics Processing Units (GPUs) are massively parallel, many-core processors with tremendous computational power and very high memory bandwidth. With the advent of general purpose programming models such as NVIDIA’s CUDA and the new standard OpenCL, general purpose programming using GPUs (GPGPU) has become very popular. However, the GPU architecture and programming model have brought along with it many new challenges and opportunities for compiler optimizations. One such classical optimization is loop unrolling. Current GPU compilers perform limited loop unrolling. In this paper, we attempt to understand the impact of loop unrolling on GPGPU programs. We develop a semi-automatic, compile-time approach for identifying optimal unroll factors for suitable loops in GPGPU programs. In addition, we propose techniques for reducing the number of unroll factors evaluated, based on the characteristics of the program being compiled and the device being compiled to. We use these techniques to evaluate the effect of loop unrolling on a range of GPGPU programs and show that we correctly identify the optimal unroll factors. The optimized versions run up to 70 percent faster than the unoptimized versions.
November 3, 2010 by hgpu
