high performance computing on graphics processing units: hgpu.org

This thesis addresses the design of cryptographic accelerators, ranging from the embedded system to the high-performance computing device. New techniques are proposed to allow several cryptographic algorithms to be computed by the same target. Therefore, flexibility (to support several algorithms) and scalability (to extend the features of a designed accelerator) are two keywords in all the contributions of this thesis. Among these contributions is the design of a cryptographic accelerator tailored for Field Programming Gate Arrays (FPGAs) able to support the Advanced Encryption Standard (AES) and Elliptic Curve (EC) cryptography. The desired speed-cost tradeoff can be easily tuned through reconfiguration due to the modular design of the accelerator. Another technique herein proposed is the utilization of the Residue Number System (RNS) to expose parallelism in cryptographic algorithms. This technique enables the design of efficient programmable accelerators for devices capable of providing a large degree of parallelism, namely Graphical Processing Units (GPUs). A thorough evaluation and design of massive parallel accelerators for modular arithmetic (the arithmetic that underlie many cryptographic algorithms) is accomplished in this thesis. This leverages the proposal of the Computing with the Residue Number System Framework (CRNS), which aims at the automatic implementation of fully functional cryptograhic accelerators based on FPGAs or GPUs.