The Power-Performance Tradeoffs of the Intel Xeon Phi on HPC Applications

Bo Li, Hung-Ching Chang, Shuaiwen Leon Song, Chun-Yi Su, Timmy Meyer, John Mooring, Kirk Cameron
Virginia Tech
International Workshop on Large Scale Parallel Processing (LSPP), in conjunction with IPDPS’14, 2014


   title={The Power-Performance Tradeoffs of the Intel Xeon Phi on HPC Applications},

   author={Li, Bo and Chang, Hung-Ching and Song, Shuaiwen Leon and Su, Chun-Yi and Meyer, Timmy and Mooring, John and Cameron, Kirk},



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Accelerators are used in about 13% of the current Top500 List. Supercomputers leveraging accelerators grew by a factor of 2.2x in 2012 and are expected to completely dominate the Top500 by 2015. Though most of these deployments use NVIDIA GPGPU accelerators, Intel’s Xeon Phi architecture will likely grow in popularity in the coming years. Unfortunately, there are few studies analyzing the performance and energy efficiency of systems leveraging the Intel Xeon Phi. We extend our systemic measurement methodology to isolate system power by component including accelerators. We use this methodology to present a detailed study of the performance-energy tradeoffs of the Xeon Phi architecture. We demonstrate the portability of our approach by comparing our Xeon Phi results to the Intel multicore Sandy Bridge host processor and the NVIDIA Tesla GPU for a wide range of HPC applications. Our results help explain limitations in the power-performance scalability of HPC applications on the current Intel Xeon Phi architecture.
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