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A Survey Of Techniques for Architecting DRAM Caches

Sparsh Mittal, Jeffrey Vetter
Oak Ridge National Lab, USA
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2015

@article{mittal2015DRAMcacheSurvey,

   title={A Survey Of Techniques for Architecting DRAM Caches},

   year={2015},

   author={Sparsh Mittal and Jeffrey Vetter},

   journal={IEEE Transactions on Parallel and Distributed Systems (TPDS)},

   doi={10.1109/TPDS.2015.2461155},

   url={https://www.academia.edu/14740788/A_Survey_Of_Techniques_for_Architecting_DRAM_Caches},

   keywords={Review, classification, last level cache, die-stacking, 3D, stacked DRAM, bandwidth wall, extreme-scale system, architectural techniques}

}

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Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture. In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. Efficient integration of DRAM caches in mainstream computing systems, however, also presents several challenges and several recent techniques have been proposed to address them. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.
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