Writing a performance-portable matrix multiplication

Jorge F. Fabeiro, Diego Andrade, Basilio B. Fraguela
Computer Architecture Group, Universidade da Coruna, Spain
Parallel Computing, 52:65-77, 2016


   title={Writing a performance-portable matrix multiplication},

   author={Fabeiro, Jorge F and Andrade, Diego and Fraguela, Basilio B},

   journal={Parallel Computing},




There are several frameworks that, while providing functional portability of code across different platforms, do not automatically provide performance portability. As a consequence, programmers have to hand-tune the kernel codes for each device. The Heterogeneous Programming Library (HPL) is one of these libraries, but it has the interesting feature that the kernel codes, which implement the computation to be performed, are generated at runtime. This run-time code generation (RTCG) capability can be used, in conjunction with generic parameterized algorithms, to write performance-portable codes. In this paper we explain how these techniques can be applied to a matrix multiplication algorithm. The performance of our implementation is compared to two state-of-the-art adaptive implementations, clBLAS and ViennaCL, on four different platforms, achieving average speedups with respect to them of 1.74 and 1.44, respectively.
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