Multi-kernel Data Partitioning with Channel on OpenCL-based FPGAs

Zeke Wang, Johns Paul, Bingsheng He, Wei Zhang
National University of Singapore, Singapore
National University of Singapore, Technical Report, 2017


   title={Multi-kernel Data Partitioning with Channel on OpenCL-based FPGAs (Technical Report)},

   author={Wang, Zeke and Paul, Johns and He, Bingsheng and Zhang, Wei},



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FPGAs have been widely used to accelerate relational database applications, due to their high throughput and high energy efficiency. However, hardware programmer needs to leverage hardware description languages (HDLs) to program FPGAs. Since HDL is cycle-sensitive and error-prone, deep knowledge about hardware design and hands-on experiences are required to guarantee a successful design on FPGA, impeding a more widespread adoption of FPGAs. Fortunately, FPGA vendors (such as Altera) have started to address the programmability issues of FPGAs via OpenCL SDKs. In this paper, we analyze the performance of relational database applications on FPGAs using OpenCL. In particular, we study how to improve the performance of data partitioning, which is a very important building block in relational database. Since the data partitioning casuses random memory accesses, it is time-consuming, and then it has been the major bottleneck for database operators such as partitioned hash join. In particular, we import the state-of-the-art OpenCL implementation of data partitioning from OmniDB, which was originally designed and optimized for CPUs/GPUs, and we find that this implementation suffers from both lock overhead and memory bandwidth overhead. Accordingly, we present a multikernel approach to address the lock overhead by leveraging two emerging features (task kernel and channel) from Altera OpenCL SDK. In order to reduce the memory bandwidth overhead, onchip buckets are used to reduce the number of random global memory transactions. In order to improve the issue rate of the producer stage, we propose the converging technology which can gather tuples from multiple channels and then deliver one tuple each time. Since all the optimizations require FPGA resources to implement, we further develop an FPGA-specific cost model to guide the parameter configuration. We evaluate the proposed design on a recent OpenCL-based FPGA. We have applied our optimized partitioning method to a number of data processing tasks, including hash join, histogram and hash search. Our experimental results demonstrate that our cost model can accurately guide the user to determine the optimal parameter combination for data partitioning and the optimal parameter combination can achieve 16.6X speedup over the default multi-threaded implementation.
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