Design of Hardware Accelerator for Lempel-Ziv 4 (LZ4) Compression
Dept. of Electronic Engineering, Seoul National Univ. of Science and Technology 232 Gongreung-ro, Nowon-gu, Seoul, 139-743, Korea
IEICE Electronics Express, Article ID: 14.20170399, 2017
Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.
May 22, 2017 by hgpu
