Understanding software approaches for GPGPU reliability

Martin Dimitrov, Mike Mantor, Huiyang Zhou
University of Central Florida, Orlando
In GPGPU-2: Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units (2009), pp. 94-104


   title={Understanding software approaches for GPGPU reliability},

   author={Dimitrov, M. and Mantor, M. and Zhou, H.},

   booktitle={Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units},





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Even though graphics processors (GPUs) are becoming increasingly popular for general purpose computing, current (and likely near future) generations of GPUs do not provide hardware support for detecting soft/hard errors in computation logic or memory storage cells since graphics applications are inherently fault tolerant. As a result, if an error occurs in GPUs during program execution, the results could be silently corrupted, which is not acceptable for general purpose computations. To improve the fidelity of general purpose computation on GPUs (GPGPU), we investigate software approaches to perform redundant execution. In particular, we propose and study three different, application-level techniques. The first technique simply executes the GPU kernel program twice, and thus achieves roughly half of the throughput of a non-redundant execution. The next two techniques interleave redundant execution with the original code in different ways to take advantage of the parallelism between the original code and its redundant copy. Furthermore, we evaluate the benefits of providing hardware support, including ECC/parity protection to on-chip and off-chip memories, for each of the software techniques. Interestingly, our findings, based on six commonly used applications, indicate that the benefits of complex software approaches are both application and architecture dependent. The simple approach, which executes the kernel twice, is often sufficient and may even outperform the complex ones. Moreover, we argue that the cost is not justified to protect memories with ECC/parity bits.
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