17709

Architecting SOT-RAM Based GPU Register File

Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Tahoori, Adwait Jog and Jeffrey Vetter
Indian Institute of Technology Hyderabad
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

@inproceedings{ref91,

   title={"ArchitectingSOT-RAMBasedGPURegisterFile"},

   year={"2017"},

   author={"SparshMittalandRajendraBishnoiandFabianOborilandHaonanWangandMehdiTahooriandAdwaitJogandJeffreyVetter"},

   booktitle={"IEEEComputerSocietyAnnualSymposiumonVLSI(ISVLSI)"},

   address={"Germany"},

   keywords={"GPU}

}

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With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.
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