high performance computing on graphics processing units: hgpu.org

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Architecting SOT-RAM Based GPU Register File

Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Tahoori, Adwait Jog and Jeffrey Vetter

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Tags: GPU, microarchitecture, non-volatile memory, Register file

October 24, 2017 by sparsh0mittal

Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File

Sparsh Mittal, Haonan Wang, Adwait Jog and Jeffrey Vetter

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Tags: GPU, Register file, Reliability

November 1, 2016 by sparsh0mittal

A Survey of Techniques for Architecting Processor Components using Domain Wall Memory

Sparsh Mittal

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Tags: cache, cpu, energy, GPU, main memory, Performance, Register file, Reliability

September 5, 2016 by sparsh0mittal

A Survey of Techniques for Designing and Managing CPU Register File

Sparsh Mittal

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Tags: cpu, Performance, Register file, survey

July 8, 2016 by sparsh0mittal

A Survey of Techniques for Architecting and Managing GPU Register File

Sparsh Mittal

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Tags: Energy efficiency, GPU, nVidia, Performance, Power, Register file, Reliability, Research, survey

March 22, 2016 by sparsh0mittal

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Advanced evolutionary computation library built directly on top of PyTorch, created at NNAISENSE

EvoTorch: Scalable Evolutionary Computation in Python

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high performance computing on graphics processing units: hgpu.org

Architecting SOT-RAM Based GPU Register File

Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File

A Survey of Techniques for Architecting Processor Components using Domain Wall Memory

A Survey of Techniques for Designing and Managing CPU Register File

A Survey of Techniques for Architecting and Managing GPU Register File

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BAT: A standardized benchmark suite for auto-tuners

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Advanced evolutionary computation library built directly on top of PyTorch, created at NNAISENSE

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