high performance computing on graphics processing units: hgpu.org

Hardware acceleration is considered a powerful tool in parallel-computing, able to overcome the limitations imposed by sequential execution of software applications and, at the same time, provide energy-efficient alternatives to other parallel computing platforms such as GPUs. However, the increasing application complexity makes it unaffordable to map algorithms directly into HDL. Hence, High-Level Synthesis tools can be used to leverage the design of hardware accelerators from high-level programming languages such as C/C++ or OpenCL. In this paper, the use of High-Level Synthesis tools to generate hardware accelerators for applications with significant data-level parallelism is evaluated. Multiple copies of the same accelerator are used to analyze performance scalability in two different scenarios: high-performance embedded computing, and small-scale datacenter. In the former, Vivado HLS is used to generate accelerators from C and OpenCL code, which are then compared to several software-based multicore alternatives. In the latter, accelerators are seamlessly integrated using SDAccel, and the OpenCL-based description is also used to establish comparisons with other parallel computing platforms (GPUs). Experimental tests show promising results in the high-performance embedded computing scenario, where hardware-based processing outperforms its software-based counterparts. However, the results obtained in the small-scale datacenter scenario show that FPGA-based acceleration using OpenCL is currently no match for high-end GPU devices in certain applications.