Delivering Performance-Portable Stencil Computations on CPUs and GPUs Using Bricks

Tuowen Zhao, Samuel Williams, Mary Hall, Hans Johansen
School of Computing, University of Utah
International Workshop on Performance, Portability, and Productivity in HPC (P3HPC), 2018


   title={Delivering Performance-Portable Stencil Computations on CPUs and GPUs Using Bricks},

   author={Zhao, Tuowen and Williams, Samuel and Hall, Mary and Johansen, Hans},



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Achieving high performance on stencil computations poses a number of challenges on modern architectures. The optimization strategy varies significantly across architectures, types of stencils, and types of applications. The standard approach to adapting stencil computations to different architectures, used by both compilers and application programmers, is through the use of iteration space tiling, whereby the data footprint of the computation and its computation partitioning are adjusted to match the memory hierarchy and available parallelism of different platforms. In this paper, we explore an alternative performance portability strategy for stencils, a data layout library for stencils called bricks, that adapts data footprint and parallelism through fine-grained data blocking. Bricks are designed to exploit the inherent multi-dimensional spatial locality of stencils, facilitating improved code generation that can adapt to CPUs or GPUs, and reducing pressure on the memory system. We demonstrate that bricks are performance-portable across CPU and GPU architectures and afford performance advantages over various tiling strategies, particularly for modern multi-stencil and highorder stencil computations. For a range of stencil computations, we achieve high performance on both the Intel Knights Landing (Xeon Phi) and Skylake (Xeon) CPUs as well as the NVIDIA P100 (Pascal) GPU delivering up to a 5x speedup against tiled code.
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