A Sorting Library for FPGA Implementation in OpenCL Programming
University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, 305-8577 Japan
11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), 2021
@inproceedings{kobayashi2021sorting,
title={A Sorting Library for FPGA Implementation in OpenCL Programming},
author={Kobayashi, Ryohei and Miura, Kento and Fujita, Norihisa and Boku, Taisuke and Amagasa, Toshiyuki},
booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies},
pages={1–6},
year={2021}
}
In this study, we focus on data sorting, which is a basic arithmetic operation, and we present a sorting library that can be used with the OpenCL programming model for field-programmable gate arrays (FPGAs). Our sorting library is built by combining three hardware sorting algorithms. It consumes more than twice the overall hardware resources compared to the merge sort restructured for the OpenCL programming model for FPGAs. However, its operating frequency is 1.09x higher and its sorting throughput is three orders of magnitude greater than the baseline.
July 4, 2021 by hgpu
