author={Ghielmetti, Nicolò and Loncar, Vladimir and Pierini, Maurizio and Roed, Marcel and Summers, Sioni and Aarrestad, Thea and Petersson, Christoffer and Linander, Hampus and Ngadiuba, Jennifer and Lin, Kelvin and Harris, Philip},
keywords={Computer Vision and Pattern Recognition (cs.CV), Hardware Architecture (cs.AR), Machine Learning (cs.LG), Instrumentation and Detectors (physics.ins-det), Machine Learning (stat.ML), FOS: Computer and information sciences, FOS: Computer and information sciences, FOS: Physical sciences, FOS: Physical sciences},
title={Real-time semantic segmentation on FPGAs for autonomous vehicles with hls4ml},
In this paper, we investigate how field programmable gate arrays can serve as hardware accelerators for real-time semantic segmentation tasks relevant for autonomous driving. Considering compressed versions of the ENet convolutional neural network architecture, we demonstrate a fully-on-chip deployment with a latency of 4.9 ms per image, using less than 30% of the available resources on a Xilinx ZCU102 evaluation board. The latency is reduced to 3 ms per image when increasing the batch size to ten, corresponding to the use case where the autonomous vehicle receives inputs from multiple cameras simultaneously. We show, through aggressive filter reduction and heterogeneous quantization-aware training, and an optimized implementation of convolutional layers, that the power consumption and resource utilization can be significantly reduced while maintaining accuracy on the Cityscapes dataset.
