high performance computing on graphics processing units: hgpu.org

We discuss three SYCL realisations of a simple Finite Volume scheme over multiple Cartesian patches. The realisation flavours differ in the way how they map the compute steps onto loops and tasks: We compare an implementation which is exclusively using a cascade of for-loops to a version which uses nested parallelism, and finally benchmark these against a version which models the calculations as task graph. Our work proposes realisation idioms to realise these flavours within SYCL. The idioms translate to some degree to other GPGPU programming techniques, too. Our preliminary results suggest that SYCL’s capability to model calculations via tasks or nested parallelism does not yet allow such realisations to outperform their counterparts using exclusively data parallelism.